Upstream Synchronization - Partial [v0.19]#69
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roma-jam merged 5 commits intorelease/v0.19from Nov 24, 2025
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~~Closed due to the release of the version 0.20.0. ~~ Re-opened with solution:
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This was referenced Nov 20, 2025
dwc2 requires manually toggle Even/Odd bit manually for ISO IN transfer, that's poses a problem when bInterval > 1 mainly for audio class, as the moment the transfer is scheduled, we don't know when the host will issue IN token (bInterval vs bRefresh schenanigans). Linux driver use NAK interrupt to detect when the host is sending IN token and toggle the Even/Odd bit accordingly based on the current frame number and bInterval. However on ST's stripped down DWC2 FS controller (e.g STM32F4, STM32F7), NAK interrupt is not supported, even it's marked as always present in DWC2 databook. NAK interrupt is only supported on HS controller with external PHY. Instead I schedule all ISO IN transfer for next frame, if the transfer failed, incomplete isochronous IN transfer interrupt will be triggered and we can relaunch the transfer. This is a combination of 4 commits, including: - dwc2: support ISO IN transfer when bInterval > 1 - Retry until bInterval - Simply restart the transfer - extract to handle_incomplete_iso_in() for readability Signed-off-by: HiFiPhile <admin@hifiphile.com>
This is a combination of 3 commits: - Fix preset with espressif - dcd/dwc2: fix enumration when EP0 size=8 - dcd/dwc2: cleanup previous pending EP0 IN transfer if a SETUP packet is received Signed-off-by: Mengsk <admin@hifiphile.com>
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This was referenced Nov 26, 2025
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Description
This PR contain cherry-picked changes from the upstream to solve the limitations in #68
Goal
2 instead of the previous releases: v0.19.010.20.0, which are not stable yet and will take place in the releasev0.20.0~1from here: Upstream synchronization [v0.20] #73Changes
Fix EP0 multi-packet transfer logic (potential 3295)moved to thev0.20.0~1releaseRelates
Verification
ESP-IDF USB Examples Run isn't available in CI. Verified manually.