Fourth year computer engineering student at Cal Poly.
My interests are in RTL, digital design, computer architecture, and ASIC development.
-
18:36
(UTC -12:00) - in/saul-rodriguez04
Pinned Loading
-
fib_acc
fib_acc PublicA Fibonacci ASIC accelerator built using system verilog and open-source EDA tools.
C++
-
mat_mul_sys_arr
mat_mul_sys_arr PublicImplementation of Matrix Multiplication in hardware using a systolic architecture
SystemVerilog
-
-
Vortex-ASIC
Vortex-ASIC PublicTaking a single Vortex core and L1 cache into an ASIC using open-source EDA tools.
SystemVerilog
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.