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@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 6.8k 856

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 431 150

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 92 41

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 166 91

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 68 64

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 303 120

Repositories

Showing 10 of 85 repositories
  • env-scripts Public

    Scripts for XiangShan

    OpenXiangShan/env-scripts’s past year of commit activity
    Tcl 17 21 0 5 Updated Jan 2, 2026
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan’s past year of commit activity
    Scala 6,823 MulanPSL-2.0 856 22 106 Updated Jan 2, 2026
  • YunSuan Public

    This repo includes XiangShan's function units

    OpenXiangShan/YunSuan’s past year of commit activity
    Scala 28 MulanPSL-2.0 15 0 1 Updated Jan 2, 2026
  • XiangShan-Design-Doc Public

    Documentation for XiangShan Design

    OpenXiangShan/XiangShan-Design-Doc’s past year of commit activity
    Markdown 38 CC-BY-4.0 16 11 (2 issues need help) 9 Updated Jan 2, 2026
  • GEM5 Public
    OpenXiangShan/GEM5’s past year of commit activity
    C++ 122 BSD-3-Clause 58 22 50 Updated Dec 31, 2025
  • xs-env Public

    XiangShan Frontend Develop Environment

    OpenXiangShan/xs-env’s past year of commit activity
    Shell 68 64 3 2 Updated Dec 31, 2025
  • Utility Public
    OpenXiangShan/Utility’s past year of commit activity
    Scala 15 24 0 7 Updated Dec 31, 2025
  • difftest Public

    Modern co-simulation framework for RISC-V CPUs

    OpenXiangShan/difftest’s past year of commit activity
    C++ 166 MulanPSL-2.0 91 7 7 Updated Dec 31, 2025
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU’s past year of commit activity
    C 303 120 21 13 Updated Dec 30, 2025
  • XiangShan-User-Guide Public

    The User Guide of XiangShan.

    OpenXiangShan/XiangShan-User-Guide’s past year of commit activity
    Markdown 15 CC-BY-4.0 8 2 1 Updated Dec 30, 2025
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Most used topics

chisel risc-v