From a435a140613cf29e0d39b0df15f16b0ebf0ba757 Mon Sep 17 00:00:00 2001 From: Gopi Botlagunta Date: Wed, 18 Feb 2026 20:00:07 +0530 Subject: [PATCH] FROMLIST: arm64: dts: qcom: lemans-evk: Enable mdss1 display Port This change enables DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to edp2 and edp3. Link: https://lore.kernel.org/lkml/20260219-enable-edp2-3-lemans-evk-mezzanine-v1-1-969316806538@oss.qualcomm.com/ Signed-off-by: Gopi Botlagunta --- .../boot/dts/qcom/lemans-evk-mezzanine.dtso | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-mezzanine.dtso index 4fab96ba873c..52f890fa9ab3 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-mezzanine.dtso @@ -11,6 +11,30 @@ &{/} { model = "Qualcomm Technologies, Inc. Lemans-evk Mezzanine"; + dp2-connector { + compatible = "dp-connector"; + label = "eDP2"; + type = "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "eDP3"; + type = "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_out>; + }; + }; + }; + vreg_0p9: regulator-vreg-0p9 { compatible = "regulator-fixed"; regulator-name = "VREG_0P9"; @@ -179,6 +203,43 @@ }; }; + +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 = <&dp2_hot_plug_det>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 = <&dp3_hot_plug_det>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp2_connector_in>; +}; + +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp3_connector_in>; +}; + +&mdss1_dp0_phy { + status = "okay"; +}; + +&mdss1_dp1_phy { + status = "okay"; +}; + &pcie0 { iommu-map = <0x0 &pcie_smmu 0x0 0x1>, <0x100 &pcie_smmu 0x1 0x1>, @@ -273,6 +334,18 @@ }; &tlmm { + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins = "gpio104"; + function = "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins = "gpio103"; + function = "edp3_hot"; + bias-disable; + }; + ethernet1_default: ethernet1-default-state { ethernet1-mdc-pins { pins = "gpio20";