From e73999ce410fefd11d0fe98d30f2fd15f2f9566b Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 16 Feb 2026 10:28:31 +0530 Subject: [PATCH 01/12] FROMLIST: regulator: core: Remove regulator supply_name length limit When creating the regulator object, associated with a consumer device, the supply_name is string formatted into a statically sized buffer on the stack, then strdup()'ed onto the heap. Not only is the dance on the stack unnecessary, but when the device's name is long we might not fit the constructed supply_name in the fixed 64 byte buffer on the stack. One such case can be seen on the Qualcomm Rb3Gen2 board, where we find a PCIe controller, with a PCIe switch, with a USB controller, with a USB hub, consuming a regulator. In this example the dev->kobj.name itself is 62 characters long. Drop the temporary buffer on the stack and kasprintf() the string directly on the heap, both to simplify the code, and to remove the length limitation. Link:https://lore.kernel.org/linux-arm-msm/177091226767.237262.6699917364293122804.b4-ty@kernel.org/T/#t Signed-off-by: Bjorn Andersson Signed-off-by: Akash Kumar --- drivers/regulator/core.c | 10 +--------- drivers/usb/host/pci-quirks.c | 5 +++++ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index b38b087eccfd7..c62f3358ddfd0 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1882,15 +1882,7 @@ static struct regulator *create_regulator(struct regulator_dev *rdev, lockdep_assert_held_once(&rdev->mutex.base); if (dev) { - char buf[REG_STR_SIZE]; - int size; - - size = snprintf(buf, REG_STR_SIZE, "%s-%s", - dev->kobj.name, supply_name); - if (size >= REG_STR_SIZE) - return NULL; - - supply_name = kstrdup(buf, GFP_KERNEL); + supply_name = kasprintf(GFP_KERNEL, "%s-%s", dev->kobj.name, supply_name); if (supply_name == NULL) return NULL; } else { diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index 0404489c2f6a9..bbf7606348d85 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c @@ -1269,6 +1269,11 @@ static void quirk_usb_early_handoff(struct pci_dev *pdev) if (pdev->vendor == 0x184e) /* vendor Netlogic */ return; + /* Skip handoff for Renesas PCI USB controller on QCOM SOC */ + if ((pdev->vendor == PCI_VENDOR_ID_RENESAS) && + (pcie_find_root_port(pdev)->vendor == PCI_VENDOR_ID_QCOM)) + return; + /* * Bypass the Raspberry Pi 4 controller xHCI controller, things are * taken care of by the board's co-processor. From b7cfde3e02fa6b5ec3345aaec9afb2d7eb2bde69 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:29 +0100 Subject: [PATCH 02/12] FROMLIST: dt-bindings: usb: document the Renesas UPD720201/UPD720202 USB 3.0 xHCI Host Controller Document the Renesas UPD720201/UPD720202 USB 3.0 xHCI Host Controller, which connects over PCIe and requires specific power supplies to start up. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring (Arm) Signed-off-by: Akash Kumar --- .../bindings/usb/renesas,upd720201-pci.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/renesas,upd720201-pci.yaml diff --git a/Documentation/devicetree/bindings/usb/renesas,upd720201-pci.yaml b/Documentation/devicetree/bindings/usb/renesas,upd720201-pci.yaml new file mode 100644 index 0000000000000..34acee62cdd21 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/renesas,upd720201-pci.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/renesas,upd720201-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UPD720201/UPD720202 USB 3.0 xHCI Host Controller (PCIe) + +maintainers: + - Neil Armstrong + +description: + UPD720201 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. + The UPD720202 supports up to two downstream ports, while UPD720201 + supports up to four downstream USB 3.0 rev1.0 ports. + +properties: + compatible: + const: pci1912,0014 + + reg: + maxItems: 1 + + avdd33-supply: + description: +3.3 V power supply for analog circuit + + vdd10-supply: + description: +1.05 V power supply + + vdd33-supply: + description: +3.3 V power supply + +required: + - compatible + - reg + - avdd33-supply + - vdd10-supply + - vdd33-supply + +allOf: + - $ref: usb-xhci.yaml + +additionalProperties: false + +examples: + - | + pcie@0 { + reg = <0x0 0x1000>; + ranges = <0x02000000 0x0 0x100000 0x10000000 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + usb-controller@0 { + compatible = "pci1912,0014"; + reg = <0x0 0x0 0x0 0x0 0x0>; + avdd33-supply = <&avdd33_reg>; + vdd10-supply = <&vdd10_reg>; + vdd33-supply = <&vdd33_reg>; + }; + }; From 76a5c82c9b668d9e0ee0f26c5ae05c90f8bc3523 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:30 +0100 Subject: [PATCH 03/12] FROMLIST: pci: pwrctrl: slot: fix dev_err_probe() usage The code was not returning dev_err_probe() but dev_err_probe() returns the error code, so simplify the code. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Suggested-by: Bartosz Golaszewski Signed-off-by: Neil Armstrong Reviewed-by: Bartosz Golaszewski Signed-off-by: Akash Kumar --- drivers/pci/pwrctrl/slot.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d89..08e53243cdbd5 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -40,17 +40,14 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev) ret = of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); - if (ret < 0) { - dev_err_probe(dev, ret, "Failed to get slot regulators\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get slot regulators\n"); slot->num_supplies = ret; ret = regulator_bulk_enable(slot->num_supplies, slot->supplies); if (ret < 0) { - dev_err_probe(dev, ret, "Failed to enable slot regulators\n"); regulator_bulk_free(slot->num_supplies, slot->supplies); - return ret; + return dev_err_probe(dev, ret, "Failed to enable slot regulators\n"); } ret = devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, @@ -59,10 +56,9 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev) return ret; clk = devm_clk_get_optional_enabled(dev, NULL); - if (IS_ERR(clk)) { + if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable slot clock\n"); - } pci_pwrctrl_init(&slot->ctx, dev); From 56d1491718a56957de03cdcbfff475fec1d79384 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:31 +0100 Subject: [PATCH 04/12] FROMLIST: pci: pwrctrl: rename pci-pwrctrl-slot as generic The driver is pretty generic and would fit for either PCI Slots or PCI devices connected to PCI ports, so rename the driver and module as pci-pwrctrl-generic. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Suggested-by: Manivannan Sadhasivam Signed-off-by: Neil Armstrong Signed-off-by: Akash Kumar --- drivers/pci/pwrctrl/Kconfig | 8 ++++---- drivers/pci/pwrctrl/Makefile | 4 ++-- drivers/pci/pwrctrl/{slot.c => generic.c} | 0 3 files changed, 6 insertions(+), 6 deletions(-) rename drivers/pci/pwrctrl/{slot.c => generic.c} (100%) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index 32e3c72755293..42f04ab1c98a9 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -11,12 +11,12 @@ config PCI_PWRCTRL_PWRSEQ select POWER_SEQUENCING select PCI_PWRCTRL -config PCI_PWRCTRL_SLOT - tristate "PCI Power Control driver for PCI slots" +config PCI_PWRCTRL_GENERIC + tristate "Generic PCI Power Control driver for PCI slots" select PCI_PWRCTRL help - Say Y here to enable the PCI Power Control driver to control the power - state of PCI slots. + Say Y here to enable the generic PCI Power Control driver to control + the power state of PCI slots. This is a generic driver that controls the power state of different PCI slots. The voltage regulators powering the rails of the PCI slots diff --git a/drivers/pci/pwrctrl/Makefile b/drivers/pci/pwrctrl/Makefile index 13b02282106c2..f6bb4fb9a410b 100644 --- a/drivers/pci/pwrctrl/Makefile +++ b/drivers/pci/pwrctrl/Makefile @@ -5,7 +5,7 @@ pci-pwrctrl-core-y := core.o obj-$(CONFIG_PCI_PWRCTRL_PWRSEQ) += pci-pwrctrl-pwrseq.o -obj-$(CONFIG_PCI_PWRCTRL_SLOT) += pci-pwrctrl-slot.o -pci-pwrctrl-slot-y := slot.o +obj-$(CONFIG_PCI_PWRCTRL_GENERIC) += pci-pwrctrl-generic.o +pci-pwrctrl-generic-y := generic.o obj-$(CONFIG_PCI_PWRCTRL_TC9563) += pci-pwrctrl-tc9563.o diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/generic.c similarity index 100% rename from drivers/pci/pwrctrl/slot.c rename to drivers/pci/pwrctrl/generic.c From 7fb9a3d3642058326b4b39d9a4af9353491ba83f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:32 +0100 Subject: [PATCH 05/12] FROMLIST: pci: pwrctrl: generic: support for the UPD720201/UPD720202 USB 3.0 xHCI Host Controller Enable the generic pwrctrl driver to control the power of the PCIe UPD720201/UPD720202 USB 3.0 xHCI Host Controller. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong Signed-off-by: Akash Kumar --- drivers/pci/pwrctrl/generic.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pwrctrl/generic.c b/drivers/pci/pwrctrl/generic.c index 08e53243cdbd5..49bb890cada17 100644 --- a/drivers/pci/pwrctrl/generic.c +++ b/drivers/pci/pwrctrl/generic.c @@ -44,12 +44,6 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev) return dev_err_probe(dev, ret, "Failed to get slot regulators\n"); slot->num_supplies = ret; - ret = regulator_bulk_enable(slot->num_supplies, slot->supplies); - if (ret < 0) { - regulator_bulk_free(slot->num_supplies, slot->supplies); - return dev_err_probe(dev, ret, "Failed to enable slot regulators\n"); - } - ret = devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, slot); if (ret) @@ -60,6 +54,12 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable slot clock\n"); + ret = regulator_bulk_enable(slot->num_supplies, slot->supplies); + if (ret < 0) { + regulator_bulk_free(slot->num_supplies, slot->supplies); + return dev_err_probe(dev, ret, "Failed to enable slot regulators\n"); + } + pci_pwrctrl_init(&slot->ctx, dev); ret = devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx); @@ -73,6 +73,10 @@ static const struct of_device_id pci_pwrctrl_slot_of_match[] = { { .compatible = "pciclass,0604", }, + /* Renesas UPD720201/UPD720202 USB 3.0 xHCI Host Controller */ + { + .compatible = "pci1912,0014", + }, { } }; MODULE_DEVICE_TABLE(of, pci_pwrctrl_slot_of_match); From b8cdcf437ef1fc8b1f6242e86e960af1cbf4452a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:33 +0100 Subject: [PATCH 06/12] FROMLIST: arm64: defconfig: enable pci-pwrctrl-generic as module Enable the generic power control driver module since it's required to power up the PCIe USB3 controller found on the Ayaneo Pocket S2 gaming console. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong Acked-by: Manivannan Sadhasivam Signed-off-by: Akash Kumar --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3ecc20978dc1d..1bcbc90e32778 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -249,6 +249,7 @@ CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_PWRCTRL_GENERIC=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER_USER_HELPER=y From 1ca9cf31d856ca0096a36f9b16d35c53ead677a4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:34 +0100 Subject: [PATCH 07/12] FROMLIST: dt-binding: vendor-prefixes: document the Ayaneo brand Document the Ayaneo from the Anyun Intelligent Technology (Hong Kong) Co., Ltd company. Website: https://www.ayaneo.com/product/ayaneobrand.html Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Signed-off-by: Akash Kumar --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba9..7fa32190761b6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -211,6 +211,8 @@ patternProperties: description: Axiado Corporation "^axis,.*": description: Axis Communications AB + "^ayaneo,.*": + description: Anyun Intelligent Technology (Hong Kong) Co., Ltd "^azoteq,.*": description: Azoteq (Pty) Ltd "^azw,.*": From bd5b9c61a99e2e018bee5a3ddc9e934c55c5764b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:35 +0100 Subject: [PATCH 08/12] FROMLIST: dt-bindings: arm: qcom: document the Ayaneo Pocket S2 Document the Qualcomm SM8650 based Ayaneo Pocket S2 gaming console. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong Acked-by: Rob Herring (Arm) Signed-off-by: Akash Kumar --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b56fbf968197a..4ef643caf360e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1046,6 +1046,7 @@ properties: - items: - enum: + - ayaneo,pocket-s2 - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd From ba955fb0e3dd8047bd826ef08a68f1a0c58b6c34 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:36 +0100 Subject: [PATCH 09/12] FROMLIST: arm64: dts: qcom: sm8650: Add sound DAI prefix for DP Sound DAI devices exposing same set of mixers, e.g. each DisplayPort controller, need to add dedicated prefix for these mixers to avoid conflicts and to allow ALSA to properly configure given instance. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Signed-off-by: Akash Kumar --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 3b03c13539386..23495de1985a0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5686,6 +5686,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort0"; status = "disabled"; From ff70cc99891f25bf4c628ecd2e8fabb8739677c3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 6 Feb 2026 15:50:37 +0100 Subject: [PATCH 10/12] FROMGIT: arm64: dts: qcom: add basic devicetree for Ayaneo Pocket S2 gaming console Add initial Device Tree for the Ayaneo Pocket S2 gaming console based on the Qualcomm Snapdragon 8 Gen 3 platform. The design is similar to a phone without the modem, the game control is handled via a standalone controller connected to a PCIe USB controller. Display panel support will be added in a second time. Signed-off-by: KancyJoe Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Akash Kumar --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 1551 +++++++++++++++++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 46 +- 3 files changed, 1575 insertions(+), 23 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bce08f77d037e..93455a8c4d781 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -336,6 +336,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-ayaneo-pocket-s2.dtb sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts new file mode 100644 index 0000000000000..0dc994f4e48d9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -0,0 +1,1551 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2025, Kancy Joe + */ + +/dts-v1/; + +#include +#include +#include +#include "sm8650.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/delete-node/ &rmtfs_mem; +/delete-node/ &hwfence_shbuf; + +/ { + model = "AYANEO Pocket S2 (Pro)"; + compatible = "ayaneo,pocket-s2", "qcom,sm8650"; + chassis-type = "handset"; + + aliases { + serial0 = &uart15; + serial1 = &uart14; + }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + fan: fan { + compatible = "pwm-fan"; + + interrupts-extended = <&tlmm 14 IRQ_TYPE_EDGE_FALLING>; + + pwms = <&pm8550_pwm 3 50000>; + + fan-supply = <&fan_pwr>; + + #cooling-cells = <2>; + cooling-levels = <0 16 32 45 60 80 105 130 155 180 205 230 255>; + + pinctrl-0 = <&fan_int>, <&pwm_fan_ctrl_active>; + pinctrl-1 = <&pwm_fan_ctrl_sleep>; + pinctrl-names = "default", "sleep"; + }; + + fan_pwr: fan-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "fan_pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpios = <&tlmm 125 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&fan_vdd>; + + pinctrl-0 = <&fan_pwr_pins>; + pinctrl-names = "default"; + }; + + fan_vdd: fan-vdd-regulator { + compatible = "regulator-fixed"; + + regulator-name = "fan_vdd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&fan_vdd_pins>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + upd720201_avdd33_reg: upd720201-avdd33-regulator { + compatible = "regulator-fixed"; + + regulator-name = "upd720201_avdd33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&tlmm 123 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&upd720201_avdd33>; + pinctrl-names = "default"; + }; + + upd720201_vdd10_reg: upd720201-vdd10-regulator { + compatible = "regulator-fixed"; + + regulator-name = "upd720201_vdd10"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&upd720201_vdd10>; + pinctrl-names = "default"; + }; + + upd720201_vdd33_reg: upd720201-vdd33-regulator { + compatible = "regulator-fixed"; + + regulator-name = "upd720201_vdd33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&upd720201_vdd33>; + pinctrl-names = "default"; + }; + + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-APS2"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT7", "DMIC1_OUTPUT", + "TX SWR_INPUT8", "DMIC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd939x 0>, + <&swr1 0>, + <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + codec { + sound-dai = <&wcd939x 1>, + <&swr2 0>, + <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&right_spkr>, + <&left_spkr>, + <&swr3 0>, + <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dp-dai-link { + link-name = "DisplayPort Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>, <&bt_default>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s4i_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddio1p2-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_s2c_0p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p8-supply = <&vreg_s6c_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s1c_1p2>; + vdd-l12-supply = <&vreg_s6c_1p8>; + vdd-l15-supply = <&vreg_s6c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1c_1p2>; + vdd-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s1c_1p2: smps1 { + regulator-name = "vreg_s1c_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1348000>; + regulator-initial-mode = ; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = ; + }; + + vreg_s3c_0p9: smps3 { + regulator-name = "vreg_s3c_0p9"; + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vreg_s4c_1p2: smps4 { + regulator-name = "vreg_s4c_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1280000>; + regulator-initial-mode = ; + }; + + vreg_s5c_0p7: smps5 { + regulator-name = "vreg_s5c_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + vreg_s6c_1p8: smps6 { + regulator-name = "vreg_s6c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name = "vreg_l3c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name = "vreg_l3e_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name = "vreg_l1g_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name = "vreg_l3g_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l2-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "i"; + + vreg_s4i_0p85: smps4 { + regulator-name = "vreg_s4i_0p85"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name = "vreg_l1i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name = "vreg_l2i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name = "vreg_l3i_0p91"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&cpu2_top_thermal { + trips { + cpu2_active: cpu2-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu2_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu3_top_thermal { + trips { + cpu3_active: cpu3-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu3_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu4_top_thermal { + trips { + cpu4_active: cpu4-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu4_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu5_top_thermal { + trips { + cpu5_active: cpu5-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu5_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu6_top_thermal { + trips { + cpu6_active: cpu6-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu6_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu7_top_thermal { + trips { + cpu7_active: cpu7-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu7_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&gpu0_cooling_maps { + map1 { + trip = <&gpu0_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu1_cooling_maps { + map1 { + trip = <&gpu1_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu2_cooling_maps { + map1 { + trip = <&gpu2_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu3_cooling_maps { + map1 { + trip = <&gpu3_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu4_cooling_maps { + map1 { + trip = <&gpu4_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu5_cooling_maps { + map1 { + trip = <&gpu5_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu6_cooling_maps { + map1 { + trip = <&gpu6_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu7_cooling_maps { + map1 { + trip = <&gpu7_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu0_trips { + gpu0_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu1_trips { + gpu1_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu2_trips { + gpu2_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu3_trips { + gpu3_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu4_trips { + gpu4_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu5_trips { + gpu5_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu6_trips { + gpu6_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + +}; + +&gpu7_trips { + gpu7_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + status = "okay"; + + wcd_usbss: typec-mux@e { + compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg = <0xe>; + + vdd-supply = <&vreg_l15b_1p8>; + reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; +}; + +&iris { + status = "okay"; +}; + +&lpass_wsa2macro { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + status = "okay"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1i_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_port0 { + /* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */ + usb-controller@0 { + compatible = "pci1912,0014"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + avdd33-supply = <&upd720201_avdd33_reg>; + vdd10-supply = <&upd720201_vdd10_reg>; + vdd33-supply = <&upd720201_vdd33_reg>; + + pinctrl-0 = <&gamepad_pwr_en>; + pinctrl-names = "default"; + }; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3e_0p9>; + vdda-pll-supply = <&vreg_l3i_1p2>; + vdda-qref-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + power-source = <1>; + }; + + pwm_fan_ctrl_active: pwm-fan-ctrl-active-state { + pins = "gpio9"; + function = "func1"; + bias-disable; + power-source = <0>; + qcom,drive-strength = ; + }; + + pwm_fan_ctrl_sleep: pwm-fan-ctrl-sleep-state { + pins = "gpio9"; + function = "normal"; + output-high; + bias-disable; + power-source = <0>; + qcom,drive-strength = ; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source = <1>; /* 1.8 V */ + }; +}; + +&pm8550_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + label = "Power Status"; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up = <2200>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8650/ayaneo/ps2/adsp.mbn", + "qcom/sm8650/ayaneo/ps2/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8650/ayaneo/ps2/cdsp.mbn", + "qcom/sm8650/ayaneo/ps2/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&reserved_memory { + lost_reg_mem: lost-reg-mem { + reg = <0 0x9b09c000 0 0x4000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf@d4e23000 { + reg = <0 0xd4e23000 0 0x2dd000>; + no-map; + }; + + splash_region: splash-region { + label = "cont_splash_region"; + reg = <0 0xd5100000 0 0x2b00000>; + no-map; + }; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Speaker Left */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + #sound-dai-cells = <0>; + reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR3 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR3 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR3 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR3 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR3 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR3 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker Right */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + #sound-dai-cells = <0>; + reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR3 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR3 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR3 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR3 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR3 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR3 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges = <32 4>, <36 1>, <38 6>, <74 1>; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + }; + + fan_pwr_pins: fan-pwr-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fan_vdd_pins: fan-vdd-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fan_int: fan-int-state { + pins = "gpio14"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + upd720201_avdd33: upd720201-avdd33-state { + pins = "gpio123"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + upd720201_vdd10: pd720201-vdd10-state { + pins = "gpio122"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + upd720201_vdd33: upd720201-vdd33-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gamepad_pwr_en: gamepad-pwr-en-active-state { + pins = "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + + max-speed = <3200000>; + }; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1c_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C + * USB SS -> NB7VPQ904MMUTWG -> USB-C + */ + +&usb_1 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1i_0p88>; + vdda12-supply = <&vreg_l3i_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3i_1p2>; + vdda-pll-supply = <&vreg_l3g_0p91>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 23495de1985a0..d0bab54d7c329 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3882,7 +3882,7 @@ }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -7516,7 +7516,7 @@ }; }; - cpu2-top-thermal { + cpu2_top_thermal: cpu2-top-thermal { thermal-sensors = <&tsens0 5>; trips { @@ -7540,7 +7540,7 @@ }; }; - cpu3-top-thermal { + cpu3_top_thermal: cpu3-top-thermal { thermal-sensors = <&tsens0 7>; trips { @@ -7564,7 +7564,7 @@ }; }; - cpu4-top-thermal { + cpu4_top_thermal: cpu4-top-thermal { thermal-sensors = <&tsens0 9>; trips { @@ -7588,7 +7588,7 @@ }; }; - cpu5-top-thermal { + cpu5_top_thermal: cpu5-top-thermal { thermal-sensors = <&tsens0 11>; trips { @@ -7612,7 +7612,7 @@ }; }; - cpu6-top-thermal { + cpu6_top_thermal: cpu6-top-thermal { thermal-sensors = <&tsens0 13>; trips { @@ -7654,7 +7654,7 @@ }; }; - cpu7-top-thermal { + cpu7_top_thermal: cpu7-top-thermal { thermal-sensors = <&tsens1 1>; trips { @@ -7917,14 +7917,14 @@ thermal-sensors = <&tsens2 1>; - cooling-maps { + gpu0_cooling_maps: cooling-maps { map0 { trip = <&gpu0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu0_trips: trips { gpu0_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -7950,14 +7950,14 @@ thermal-sensors = <&tsens2 2>; - cooling-maps { + gpu1_cooling_maps: cooling-maps { map0 { trip = <&gpu1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu1_trips: trips { gpu1_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -7983,14 +7983,14 @@ thermal-sensors = <&tsens2 3>; - cooling-maps { + gpu2_cooling_maps: cooling-maps { map0 { trip = <&gpu2_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu2_trips: trips { gpu2_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8016,14 +8016,14 @@ thermal-sensors = <&tsens2 4>; - cooling-maps { + gpu3_cooling_maps: cooling-maps { map0 { trip = <&gpu3_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu3_trips: trips { gpu3_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8049,14 +8049,14 @@ thermal-sensors = <&tsens2 5>; - cooling-maps { + gpu4_cooling_maps: cooling-maps { map0 { trip = <&gpu4_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu4_trips: trips { gpu4_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8082,14 +8082,14 @@ thermal-sensors = <&tsens2 6>; - cooling-maps { + gpu5_cooling_maps: cooling-maps { map0 { trip = <&gpu5_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu5_trips: trips { gpu5_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8115,14 +8115,14 @@ thermal-sensors = <&tsens2 7>; - cooling-maps { + gpu6_cooling_maps: cooling-maps { map0 { trip = <&gpu6_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu6_trips: trips { gpu6_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8148,14 +8148,14 @@ thermal-sensors = <&tsens2 8>; - cooling-maps { + gpu7_cooling_maps: cooling-maps { map0 { trip = <&gpu7_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu7_trips: trips { gpu7_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; From e5a0e16631677ea33c17683f794354229fa9b8a8 Mon Sep 17 00:00:00 2001 From: Akash Kumar Date: Mon, 16 Feb 2026 17:33:46 +0530 Subject: [PATCH 11/12] FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: Enable uPD720201 and GL3590 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QCS6490 Rb3Gen2 has a Renesas μPD720201 XHCI controller hanging off the TC9563 PCIe switch, on this a Genesys Logic GL3590 USB hub provides two USB Type-A ports and an ASIX AX88179 USB 3.0 Gigabit Ethernet interface. The Renesas chip is powered by two regulators controlled through PM7250B GPIOs 1 and 4, and the power/reset pin is pulled down by PM8350C GPIO 4. The Genesys chip power is always-on, but the reset pin is controlled through TLMM GPIO 162. Describe the Renesas chip on the PCIe bus, with supplies and reset, to allow it to be brought out of reset and discovered. Then describe the two peers of the USB hub, with its reset GPIO, to allow this to be brought out of reset. The USB Type-A connectors are not described, as they are in no regard controlled by the operating system. Signed-off-by: Bjorn Andersson --- Posting this as a RFC, because it doesn't work without some hacks in the PCI pwrctrl code. It depends on Neil's work for μPD720201 pwrctrl [1], on the GL3590 work by Swati and Krisha [2], and my regulator fix [3]. With these three dependencies, the hacks in drivers/pci/pwrctrl/core.c, and firmware for the μPD720201, the primary ethernet lights up. Then in pci_pwrctrl_create_device() we assume that anything in a PCI device node, with either a -supply or port/ports property, should be a platform_device. When the USB bus(es) of the μPD720201 shows up, it again registers this platform_device. It seems that of_platform_device_create() saves us and does an early exit, but by "accident". __pci_pwrctrl_power_on_device() and __pci_pwrctrl_power_off_device() on the other hand, they happily pick up the non-NULL drvdata, which is of type struct onboard_dev, to call the power_on() and power_off() methods. Link: https://lore.kernel.org/all/20260212-rb3gen2-upd-gl3590-v1-1-18fb04bb32b0@oss.qualcomm.com/ Signed-off-by: Bjorn Andersson Signed-off-by: Akash Kumar --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 161 +++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index b66bbdc561d05..a1b4282bccf6c 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -262,6 +262,28 @@ regulator-max-microvolt = <3700000>; }; + vreg_pcie0_1p05: regulator-pcie0-1p05v { + compatible = "regulator-fixed"; + regulator-name = "PCIE0_1.05V"; + gpio = <&pm7250b_gpios 4 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + enable-active-high; + pinctrl-0 = <&upd_pwr_en2_state>; + pinctrl-names = "default"; + }; + + vreg_pcie0_3p3: regulator-pcie0-3p3v-dual { + compatible = "regulator-fixed"; + regulator-name = "PCIE0_3.3V_Dual"; + gpio = <&pm7250b_gpios 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + pinctrl-0 = <&upd_pwr_en1_state>; + pinctrl-names = "default"; + }; + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { compatible = "regulator-fixed"; regulator-name = "VDD_NTN_0P9"; @@ -788,6 +810,72 @@ }; }; }; + + i2c-mux@71 { + compatible = "nxp,pca9847"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + usb-hub@2d { + compatible = "smsc,usb4604"; + reg = <0x2d>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + usb-hub@2d { + compatible = "smsc,usb4604"; + reg = <0x2d>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <6>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <7>; + }; + }; }; &lpass_va_macro { @@ -910,6 +998,42 @@ device_type = "pci"; ranges; bus-range = <0x4 0xff>; + + /* Renesas μPD720201 PCIe USB3.0 Host Controller */ + usb-controller@0,0 { + compatible = "pci1912,0014"; + reg = <0x40000 0x0 0x0 0x0 0x0>; + + avdd33-supply = <&vreg_pcie0_3p3>; + vdd10-supply = <&vreg_pcie0_1p05>; + vdd33-supply = <&vreg_pcie0_3p3>; + + pinctrl-0 = <&upd_hub_rst_state>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + /* Genesys Logic GL3590 USB Hub Controller */ + gl3590_2_0: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + + reset-gpios = <&tlmm 162 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_hub_reset_state>; + pinctrl-names = "default"; + + peer-hub = <&gl3590_3_0>; + }; + + gl3590_3_0: hub@2 { + compatible = "usb5e3,625"; + reg = <2>; + + peer-hub = <&gl3590_2_0>; + }; + }; }; pcie@3,0 { @@ -970,6 +1094,17 @@ power-source = <0>; }; + upd_hub_rst_state: upd-hub-rst-state { + pins = "gpio4"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + output-high; + power-source = <0>; + }; + tc9563_rsex_n: tc9563-resx-state { pins = "gpio1"; function = "normal"; @@ -1759,6 +1894,15 @@ }; &pm7250b_gpios { + upd_pwr_en1_state: upd-pwr-en1-state { + pins = "gpio1"; + function = "normal"; + + output-enable; + input-disable; + power-source = <0>; + }; + lt9611_rst_pin: lt9611-rst-state { pins = "gpio2"; function = "normal"; @@ -1767,6 +1911,15 @@ input-disable; power-source = <0>; }; + + upd_pwr_en2_state: upd-pwr-en2-state { + pins = "gpio4"; + function = "normal"; + + output-enable; + input-disable; + power-source = <0>; + }; }; &sdc2_clk { @@ -1812,6 +1965,14 @@ function = "gpio"; bias-pull-up; }; + + usb_hub_reset_state: usb-hub-reset-state { + pins = "gpio162"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; }; &lpass_audiocc { From eb14865212b2870f82e4b3bee6bf3f8e843e4e19 Mon Sep 17 00:00:00 2001 From: Akash Kumar Date: Mon, 16 Feb 2026 17:40:09 +0530 Subject: [PATCH 12/12] QCLINUX: arm64: configs: Enable configs for uPD720201 and GL3590 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable configs to support USB typeA ports on qcs6490 rb3gen2. These configs enable Renesas μPD720201 XHCI controller and Genesys Logic GL3590 USB hub provides two USB Type-A ports and an ASIX AX88179 USB 3.0 Gigabit Ethernet interface. Signed-off-by: Akash Kumar --- arch/arm64/configs/qcom.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/qcom.config b/arch/arm64/configs/qcom.config index 5f379c86ee4d2..e2369e113b059 100644 --- a/arch/arm64/configs/qcom.config +++ b/arch/arm64/configs/qcom.config @@ -31,6 +31,7 @@ CONFIG_INPUT_UINPUT=y CONFIG_KPROBES=y CONFIG_MACVLAN=y CONFIG_MACVTAP=y +CONFIG_PCI_PWRCTRL_TC9563=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y CONFIG_PM_AUTOSLEEP=y @@ -55,6 +56,8 @@ CONFIG_TRACE_MMIO_ACCESS=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UHID=m +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_HSIC_USB4604=m CONFIG_VCPU_STALL_DETECTOR=y CONFIG_VHOST_NET=y CONFIG_VHOST_VSOCK=y